Verification and Validation Activities for Embedded Systems - A Feasibility Study on a Reading Technique for SysML Models

Erik Aceiro Antonio, Rafael Rovina, Sandra C. P. F. Fabbri

2014

Abstract

Embedded Systems play an important role on today's interconnected world. However, there is a gap in relation to Verification and Validation (V&V) activities for Embedded Systems, particularly when they are designed with SysML models. Hence, the objective of this paper is to present a feasibility study on a Reading Techniques for detecting defects in SysML models. This technique is part of a family of reading techniques for inspecting Requirement Diagrams and State Machine Diagrams which are SysML models designed along the SYSMOD development process. The definition of these techniques required the establishment of a defects taxonomy, which was based on three sources: i) the certification standards for embedded systems UL-98 and DO-178C; ii) the Failure Mode and Effects Analysis (FMEA); and iii) the syntactic and semantic elements available in the formalism of the SysML language. A feasibility study was carried out to evaluate the effectiveness and efficiency of one of the techniques. From a total of 26 subjects, 50% have found an average of 72% of defects and spent an average of 48 minutes.

Paper Citation

in Harvard Style

Aceiro Antonio E., Rovina R. and C. P. F. Fabbri S. (2014). Verification and Validation Activities for Embedded Systems - A Feasibility Study on a Reading Technique for SysML Models . In Proceedings of the 16th International Conference on Enterprise Information Systems - Volume 2: ICEIS, ISBN 978-989-758-028-4, pages 233-240. DOI: 10.5220/0004887302330240

in Bibtex Style

@conference{iceis14,
author={Erik Aceiro Antonio and Rafael Rovina and Sandra C. P. F. Fabbri},
title={Verification and Validation Activities for Embedded Systems - A Feasibility Study on a Reading Technique for SysML Models},
booktitle={Proceedings of the 16th International Conference on Enterprise Information Systems - Volume 2: ICEIS,},
year={2014},
pages={233-240},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004887302330240},
isbn={978-989-758-028-4},
}

in EndNote Style

TY - CONF
JO - Proceedings of the 16th International Conference on Enterprise Information Systems - Volume 2: ICEIS,
TI - Verification and Validation Activities for Embedded Systems - A Feasibility Study on a Reading Technique for SysML Models
SN - 978-989-758-028-4
AU - Aceiro Antonio E.
AU - Rovina R.
AU - C. P. F. Fabbri S.
PY - 2014
SP - 233
EP - 240
DO - 10.5220/0004887302330240